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Test and Design-for-Test at
Design, Automation & Test in E
urope
(DATE'11)

March 14-18, 2011
Grenoble, France

http://www.date-conference.com

CALL FOR SUBMISSIONS
Scope -- Submissions -- Submission Instructions -- Key Dates -- Additional Information

Scope

The Design, Automation & Test in Europe Conference and Exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in hardware and software design, test and manufacturing of electronic circuits and systems. The five-day event includes plenary invited papers, regular papers, panels, hot-topic sessions, tutorials and workshops, two special focus days, and a track for executives. DATE, with its many user group meetings, fringe meetings, and social events, offers a wide variety of opportunities to meet and exchange information.

Submissions on Test and Design-for-Test

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Test and Design-for-Test (DfT) in the broad sense are important topics and integral part of DATE. One of the parallel conference tracks is devoted to Test, and also tutorials, exhibition booths, and workshops cover Test and DfT. You are invited to participate in DATE’11 and send in one or more submissions of the following types.

  • Paper Submissions
    • Topic T1: Test for Defects, Variability, and Reliability
      Chairs: Sandip Kundu, Massachusetts University (USA); Bram Kruseman, NXP Semiconductors (NL)
      Defects and degradation mechanisms; physical sources of errors, incl. physical defects, signal integrity problems, PVT variations, and circuit reliability issues; design and test for robustness against PVT variations and circuit reliability; low-power testing.
    • Topic T2: Test Generation, Simulation, and Diagnosis
      Chairs: Nicola Nicolici, McMaster University (CAN); Bart Vermeulen, NXP Semiconductors (NL)
      Test pattern generation; high-level TPG; delay TPG; fault simulation; test generation for validation, debug and diagnosis; low-power TPG; TPG for memories and FPGAs.
    • Topic T3: Test for Mixed-Signal, Analog, RF, and MEMS
      Chairs: Hans Kerkhoff, University of Twente (NL); Abhijit Chatterjee, Georgia Institute of Technology (USA)
      Test, diagnosis, and tuning techniques for MS systems, MEMS, RF; defect modeling, test coverage metrics, statistical modeling, fault simulation, test generation, DfX techniques, BIST and BISR.
    • Topic T4: Test Access, Design-for-Test, Test Compression, System Test
      Chairs: Sandeep Kumar Goel, TSMC (USA); Sybille Hellebrand, Paderborn University (D)
      DfT for SOCs, SIPs, NOCs, and 3D-ICs; built-in and embedded test and diagnosis; test data compression, low-power DfT and BIST; design-for-debug, diagnosis, and manufacturability; system-level test.
    • Topic T5: On-Line Testing and Fault Tolerance
      Chairs: Dimitris Gizopoulos,University of Piraeus (GR); Cecilia Metra, Università di Bologna (IT)
      On-line and concurrent testing and diagnosis; fault tolerance; dependability; security; robust design.
  • Proposals for Special Sessions – Chair: Wolfgang Müller, Paderborn University (D)
    Special Sessions can take various forms:
    • Embedded Tutorials, providing technical education sessions for a broad audience,
    • Hot-Topic Sessions, dealing with the introduction and discussion of new R&D problems,
    • Panels, discussing visionary and/or controversial issues.
  • Proposals for Full-Day or Half-Day Tutorials– Chair: Luca Fanucci, Università di Pisa (IT) Tutorials are relevant and topical educational sessions, taught by leading experts.
  • Proposals for University Booth Presentations– Chairs: Lorena Anghel, TIMA (F); Volker Schöber, edaCentrum (D)
    Universities and research institutes can showcase their pre-commercial results and prototype demos.
  • Proposals for Presentations at the Exhibition Theatre – Chair: Jürgen Haase, edaCentrum (D)The Exhibition Theatre offers an open discussion forum at DATE’s exhibition, including panel sessions and customer testimonials.
  • Proposals for Full-Day Workshops– Chair: Nicola Nicolici, McMaster University (CAN)
    On Friday, DATE hosts a number of parallel workshops on emerging research and application topics.
  • Proposals for Fringe Meetings– Contact: Claire Cartwright, European Conferences (UK)
    A limited number of rooms is available for related open and closed meetings.

Submission Instructions

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Submission instructions for the various types of submissions are specified at:

http://www.date-conference.com

Key Dates

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Submission deadline: September 5, 2010 (papers, special sessions, tutorials, workshops)
Submission deadline: October 10, 2010 (exhibition theatre)
Notification of acceptance: November 7, 2010
Final copy deadline: December 6, 2010

Submission deadline: January 14, 2011 (university booth proposals)

Additional Information
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Erik Jan Marinissen – Test Track Chair
IMEC, Leuven, Belgium
e-mail: erik.jan.marinissen@imec.be

Enrico Macii – Program Chair
Politecnico di Torino, Italy
e-mail: enrico.macii@polito.it

Bashir Al-Hashimi – General Chair
Southampton University, UK
e-mail: bmah@ecs.soton.ac.uk
For more information, visit us on the web at: http://www.date-conference.com

The Design, Automation & Test in Europe (DATE'11 ) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Gordon W. ROBERTS
McGill University
- Canada
Tel. +1-514-398-6029
E-mail gordon.roberts@mcgill.ca

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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